1. Field of the Invention
The present invention relates to an active matrix type display. More specifically, the present invention relates a drive technique for writing a picture signal on the active matrix type display on a block by block basis.
2. Description of the Related Art
Active matrix type displays such as a liquid-crystal display (LCD) are a next generation display expected to substitute for CRTs (Cathode Ray Tubes), but the inputting of a picture signal is one-dimensionally performed. Specifically, picture data as a raster signal is written on a liquid-crystal panel on a line by line basis (scanning line by scanning line). To observe a picture in a narrow transmission band through NTSC broadcasting using ground waves or analog VCR, one dimensional signal inputting is appropriate.
As compressed digital pictures in a wide transmission band, such as those through satellite communications or DVD (digital versatile disk), are in widespread use as a signal source, these compressed pictures are encoded on a per m-row-by-n-column block basis (m and n are integers greater than 1). To present the encoded compressed signal, the encoded compressed signal needs to be decoded in a one-dimensional format. Since a frame memory is required to decode a picture signal compressed in a two dimensions of m rows by n columns, signal processing efficiency is not so high. It is preferred not to stick to a one dimensional inputting technique as the method of signal inputting in next generation displays. In other words, a method of inputting a picture signal on a per mxc3x97n block basis is more efficient. However, a two-dimensional signal inputting technique in an active matrix type display remains to be developed. On the other hand, thinner, more light-weight and lower power consumption design is required of the next generation displays. To this end, the use of a low speed clock in data transfer is effective. As for this requirement, the one-dimensional signal inputting technique is subject to a limitation in the effort of slowing the data transfer speed. The conventional one-dimensional signal input method is not necessarily an appropriate technique in the next generation display, and there is a need for a more efficient block input method. This is further discussed referring to the MPEG (Motion Picture Expert Group) technique.
FIGS. 11A and 11B diagrammatically show an MPEG data processing sequence. An input signal such as a video signal is compressed in an MPEG encoder 11. This compression is performed on a per eight-row-by-eight-column block basis. Specifically, picture data of 8xc3x978=64 dots as one block is subjected to a pixel decimation step or bit decimation step. The compressed MPEG data is processed through a packetization/bit stream circuit 12 and is the transmitted. A receiver side includes an MPEG decoder 13, which develops the compressed data into decompressed raster signal data. A large capacity frame memory 16 is required to convert two-dimensional data, which has been developed on a per block basis, into a one-dimensional raster signal.
FIG. 12 diagrammatically shows the raster signal data of one horizontal period assigned to one scanning line. A data transfer clock CK1 has a frequency of 25 MHz.
FIG. 13 diagrammatically shows an active matrix type display as one example of a conventional receiver set. The raster signal data shown in FIG. 12 is converted into an analog signal by a D/A converter 13x, and is then input to an active matrix type display. As shown, the active matrix type display includes a matrix of pixels formed between a pair of opposing substrates 4 and 5, scanning lines X arranged corresponding to the rows of pixels 3, and signal lines Y arranged corresponding to the columns of pixels 3. In the conventional art, the pixels are formed on the one substrate 4, and a counter electrode (common electrode) 8a is formed on the entire main surface of the other substrate 5. A row line driving circuit 14 and a column line driving circuit 15 are integrally mounted on the pair of substrates 4 and 5, or are arranged separately from the substrates 4 and 5. The row line driving circuit 14 includes a shift register, and is connected to each scanning line X to select the pixels on a row by row basis. The column line driving circuit 15 is connected to each signal line Y and writes a picture signal on a pixel on a selected row. In the circuit shown in FIG. 13, the column line driving circuit 15 writes the picture signal input from the D/A converter 13x on the pixels 3 substantially on a dot at a time basis, on a single row selected by the row line driving circuit 14.
Optionally, the picture signal may be written on the pixels on a plurality of rows (n) that are simultaneously selected. This technique is a multi-pixel simultaneous driving method, but is limited to a simultaneous driving of a plurality of pixels on a single selected row. FIG. 14 shows an example of picture signal supplied to the column line driving circuit 15 from the D/A converter 13. As shown, the column line driving circuit 15 receives n pieces of data in parallel, namely, data 1-data n, corresponding to n pixels to which the picture signal is simultaneously written. In this case, the transfer clock CK2 of the picture signal is reduced to CK1/n. This technique is a one dimensional writing method, and requires a large capacity frame memory to develop an original compressed image.
FIG. 15 shows an active matrix type display working on a line at a time scanning basis. Elements identical to those with reference to the conventional display working on a point at a time scanning basis and shown in FIG. 13 are designated with the same reference numerals. In the line at a time scanning method, input raster signal data is directly input to a column line driving circuit 15. The multiplexed raster signal data is demultiplexed by a demultiplexor in the column line driving circuit 15, is then latched row by row, and is converted into an analog signal by a D/A converter. On the other hand, the row line driving circuit 14 selects a row of pixels on a line at a time basis. The column line driving circuit 15 writes the picture signal, which has been latched and then D/A-converted, simultaneously on all pixels on a selected single row. This method is a typical single dimensional signal input technique.
FIG. 16 is a waveform diagram showing analog signal data output from the D/A converter in the column line driving circuit 15 shown in FIG. 15. In the line at a time scanning technique, the image data of one row on one horizontal period (1H) is successively output to the panel of the display in synchronization with the line at a time scanning operation of the row line driving circuit 14.
Accordingly, it is an object of the present invention to provide an active matrix type display working on a two-dimensional signal input scheme. To achieve this object, an active matrix type display of the present invention includes a pair of substrates, main surfaces thereof being facing with each other, a plurality of pixels two-dimensionally arranged in a matrix shape on the substrates, scanning lines arranged corresponding to the row of pixels, signal lines arranged corresponding to the column of pixels, a row line driving circuit connected to the scanning lines for selecting pixels row by row, and a column line driving circuit connected to the signal lines for writing a picture signal to the selected pixels, wherein the odd-numbered rows of pixels are assigned to one substrate, and the even-numbered rows of pixels are assigned to the other substrate, the row line driving circuit simultaneously selects the odd-numbered row pixels and the even-numbered pixels, and the column line driving circuit writes the picture signal on each of the simultaneously selected odd-numbered rows of pixels and even-numbered rows of pixels. Specifically, the row line driving circuit simultaneously selects at least a total of four rows of pixels composed of two odd-numbered rows of pixels and two even-numbered rows of pixels, the signal lines are divided into sets of four lines with one set for each column, wherein the two signal lines are arranged on the one substrate and the remaining two signal lines arranged on the other substrate, and the column line driving circuit writes a picture signal on each of the four simultaneously selected pixels assigned to the four rows of pixels, through the set of four signal lines. The column line driving circuit simultaneously applies a picture signal to sixteen signal lines assigned to at least four columns, thereby simultaneously writing the picture signal on sixteen pixels of four rows by four columns.
An active matrix type display of the present invention includes a pair of substrates, main surfaces thereof being facing with each other, a plurality of pixels two-dimensionally arranged in a matrix shape on the substrates, scanning lines arranged corresponding to the row of pixels, signal lines arranged corresponding to the column of pixels, a row line driving circuit connected to the scanning lines for selecting pixels row by row, and a column line driving circuit connected to the signal lines for writing a picture signal to the selected pixels, wherein a plurality of rows of pixels in an odd-numbered group is assigned to the one substrate, a plurality of rows of pixels in an even-numbered group is assigned to the other substrate, the signal lines are divided into sets of a plurality of lines with one set assigned to each column, signal lines, of the set, having the number equal to the number of rows in the odd-numbered group are arranged on the one substrate, and the remaining signal lines, of the set, having the number equal to the number of rows in the even-numbered group are arranged on the other substrate, and the column line driving circuit respectively writes the picture signal on each of a plurality of pixels in the odd-numbered group and the even-numbered group simultaneously selected, through each set of the plurality of signal lines per column of pixels.
An active matrix type display of the present invention includes a pair of substrates, main surfaces thereof being facing with each other, a plurality of pixels two-dimensionally arranged in a matrix shape on the substrates, scanning lines arranged corresponding to the row of pixels, signal lines arranged corresponding to the column of pixels, a row line driving circuit connected to the scanning lines for selecting pixels row by row, a column line driving circuit connected to the signal lines for writing the picture signal to the selected pixels, and a signal processing circuit supplied with a block segmented picture signal having M pixel signals in the column direction and N pixel signals in the row direction (M and N are positive integers greater than 1) and for processing the block segmented picture signal according to a block of m rows by n columns (m and n are positive integers greater than 1), the signal processing circuit outputting the processed signal in the block form to the column line driving circuit, wherein the row line driving circuit simultaneously selects m rows of pixels and the column line driving circuit simultaneously supplies the picture signal to the signal lines of n columns, and thereby picture signal is simultaneously written to pixels of m rows by n columns. Preferably, the signal processing circuit decodes the picture signal, which has been encoded on a per M-row-by-N-column block basis, into a picture signal compatible with pixels of M rows by N columns. The signal processing circuit successively processes the picture signal on the condition of m=M and n=N. The signal processing circuit successively processes the picture signal on condition that m is a measure of M.
In accordance with the present invention, two techniques are combined to accomplish a two-dimensional signal input method. In one technique, pixels and common electrode opposing to the pixels alternatingly arranged between the pair of substrates. The pixels and the common electrode may alternate every row or every two rows to a plurality of rows. The rows of pixel are alternatingly arranged between the two substrates so that at least two rows are simultaneously selected. In this arrangement, the pixels are divided into two groups, one group for the one substrate and the other group for the other substrate with the number of pixels unchanged. This arrangement is equivalent to the doubling of the number of the signal lines. The picture signal is simultaneously written on two pixels arranged in the column direction on two rows simultaneously selected. In accordance with the first technique, the number of pixels simultaneously lit is doubled. In a second technique, each substrate includes each column of pixels associated with at least two signal lines. The pixels in any given column are alternately connected to the two signal lines with one pixel connected to the first signal line, the next pixel connected to the second signal line, the third pixel connected to the first signal line, and so on. Every two scanning lines are connected together. In this way, the picture signal is written on two vertically arranged pixels on two selected rows. The second technique allows to be doubled the number of pixels which become concurrently conductive. With the first technique and the second technique combined, the number of pixels that can be simultaneously lit is quadrupled.